SH7760 Datasheet, PDF (133/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Table 5.2 Parallel-Executability
2nd Instruction
MT
EX
BR
LS
FE
CO
1st
MT
Instruction _EX
O
O
O
O
O
X
O
X
O
O
O
X
BR
O
O
X
O
O
X
LS
O
O
O
X
O
X
FE
O
O
O
O
X
X
CO
X
X
X
X
X
X
Legend:
O: Can be executed in parallel
X: Cannot be executed in parallel
5.3 Execution Cycles and Pipeline Stalling
This LSI has three basic clocks: CPU clock (Ick), bus clock (Bck), and peripheral clock (Pck).
Each hardware unit operates on one of these clocks, as follows:
• CPU clock: CPU, FPU, MMU, cache
• Bus clock: External bus controller
• Peripheral clock: Peripheral units
The frequency ratios of the three clocks are determined with the frequency control register
(FRQCR). In this section, machine cycles are based on the CPU clock unless otherwise specified.
For details on FRQCR, see section 12, Clock Pulse Generator (CPG).
Instruction execution cycles are summarized in table 5.3. Penalty cycles due to a pipeline stall are
not considered in this table.
• Issue rate: Interval between the issue of an instruction and that of the next instruction
• Latency: Interval between the issue of an instruction and the generation of its result
(completion)
• Instruction execution pattern (see figure 5.2)
• Locked pipeline stage: Pipeline stage which has been locked
• Lock start: Interval between the issue of an instruction and the start of locking (see table 5.3)
• Lock cycle: Period of locking (see table 5.3)
Rev. 1.0, 02/03, page 83 of 1294