SH7760 Datasheet, PDF (671/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

18.3.13 Sampling Register (SISMPL)
SISMPL is a 16-bit readable/writable register that sets the number of serial clock cycles per etu.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
- ^{SISM SISM SISM SISM SISM SISM SISM SISM SISM SISM SISM}
PL10 PL9 PL8 PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
Initial value: 0
0
0
0
0
0
0
1
0
1
1
1
0
0
1
1
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 11
Bit
Name

Initial
Value R/W
All 0 R
10 to 0
SISMPL H'173 R/W
10 to 0
[Legend] etu: Elementary Time Unit
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Setting for the number of serial clock cycles per etu
The number of serial clock cycles per etu is (SISMPL
value + 1). The value written to SISMPL should
always be H'0007 or greater.
18.4 Operation
The main functions of the SMI are as follows.
1. One frame consists of eight data bits and one parity bit.
2. The transmitter inserts the guardtime, specified by SIGRD and the LCB and PB bits in
SISCMR, between the end of each parity bit and the beginning of the next frame.
3. When detecting a parity error, the receiver in T = 0 mode outputs low level for 1 etu as an
error signal, after 10.5 etu has passed since the start bit was received.
4. When sampling an error signal, the transmitter in T = 0 mode automatically repeats the
disputed data after a delay of at least 2 etu.
5. Only asynchronous communication functions are supported; there is no clock-synchronized
communication function.
18.4.1 Data Format
Figure 18.2 shows the data format used by the smart card interface. The smart card interface
performs a parity check for each frame during reception.
When detecting a parity error, the receiver in T = 0 mode returns an error signal to the transmitter,
requesting data repetition. The transmitter samples error signals and repeats the disputed data.
Rev. 1.0,02/03, page 621 of 1294