SH7760 Datasheet, PDF (806/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

21.5.2 Storage Format of the Descriptor
ED (endpoint descriptor) and TD (transfer descriptor) that define each transfer transaction of the
USB host controller must be placed such that each Dword is aligned on a longword boundary
(addresses 4n to 4n + 3) of the memory. Each descriptor must be aligned on a memory address
boundary prescribed by the OpenHCI specification Ver.1.0.
21.6 Restrictions on HcRhDescriptorA
When modifying initial settings of the NOCP or OCPM bits in HcRhDescriptorA after reset, keep
the following in mind.
1. The initial values are NOCP=1 and OCPM=0, and the USB host controller does not detect
overcurrent. To use the overcurrent detection, set NOCP = 0 and OCPM = 1 simultaneously.
Modify these bits only once during USB host controller initialization. Do not modify them
more than once.
2. Making the settings in step 1 above will not change the settings in the OCI and OCIC bits in
HcRhStatus for overcurrent condition information. These bits should be ignored.
3. Making the settings in step 1 above will set HcInterruptStatus.RHSC = 1 even if a port is not in
overcurrent condition. Therefore, perform interrupt handling processing shown in figure 21.5.
Start of RHSC interrupt handling
Interrupt source is
No
set in HcRhStatus and
HcRhPortStatus1?
Yes
Perform handling for interrupt sources
indicated by HcRhStatus and
HcRhPortStatus1
Clear RHSC in HcInterruptStatus
End of RHSC interrupt handling
Figure 21.5 Example of RHSC interrupt handling
Rev. 1.0, 02/03, page 756 of 1294