SH7760 Datasheet, PDF (504/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Forced termination and
resume procedure
Disable interrupt for corresponding transfer
(if necessary)
1. To forcibly terminate DMA transfer in HAC or SSI before the specified bytes are
transferred, disable DMA in HAC or SSI that are being used.
When HAC is in use:
When SSI is in use:
HACACR.*DMA*_EN = 0
SSICR.EN = 0
[1] Stop HAC or SSI DMA transfer
[2] Set termination bit in DMAACR
DMAACR.TDS = 1 (transmitting)
DMAACR.RDS = 1 (receiving)
TDS == 0? (transmitting)
No
RDS == 0? (receiving)
With transfer terminate interrupt enabled, it is generated when the terminated
DMA stops completely.
When the DMA stop causes overrun or underrun in HAC or SSI,
the related interrupt should be generated.
To avoid interrupt generation, disable the related interrupts beforehand.
2. Setting the forced termination bit in DMAACR stops DMA in HAC or SSI.
However, it is only after the completion of the bus cycle being performed that
DMA stops completely.
Activating DMA before it completely stops will not take effect.
To know whether DMA has completely stopped, read the forced termination bit
in DMAACR. When the read value is 1, DMA has not stopped. Make sure that
the forced termination bit in DMAACR is 0 before activating DMA again.
In the receive operation, all received data may not be stored in synchronous
DRAM at the DMA forced termination since received data is temporarily stored
in FIFO first. Therefore, the forced termination bit in DMAACR will be cleared
to 0 when all received data is completely stored in synchronous DRAM.
Yes
Is transfer
resuming?
No
Transfer end
Yes
Read DMAARXTCNT when receiving or
DMAATXTCNT when trasmitting
to calculate number of transfers remained
Set transfer address and number of bytes
DMAARXDAR/DMAARXTCR (receiving)
DMAATXSAR/DMAATXTCR (transmitting)
Reactivating the related DMA
DMAACR.RDE = 1 (receiving)
DMAACR.TDE = 1 (transmitting)
Set HAC or SSI DMA again
-When HAC is in use:
HACACR.*DMA*_EN = 1
-When SSI is in use:
SSICR.DMEN = 1
Enable interrupt for corresponding transfer
(if necessary)
Transfer resume
Figure 11.34 Forced Termination and Resume Procedures for DMA Audio Transfer
Rev. 1.0, 02/03, page 454 of 1294