SH7760 Datasheet, PDF (560/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Figure 15.1 shows a block diagram of the TMU.
RESET,
STBY,etc.
TUNE0, Pck/4, Pck/16,
TUNE1 Pck/64*
TUNI2 ICPI2 TCLK
TMU
operation
controller
Prescaler
To each To channels
channel 0 to 2
TCLK
controller
Channels 0 and 1
Counter
Interrupt
controller
Channel 2
Counter
Interrupt
controller
TSTR
TCR TCOR TCNT
TCR2 TCOR2 TCNT2 TCPR2
Bus interface
Peripheral bus
Note: * Internal signals with 1/4, 1/16, or 1/64 of the Pck frequency and supplied to the on-chip peripheral modules.
Legend:
TSTR : Timer start register
TCOR : Timer constant register
TCNT : Timer counter
TCR : Timer control register
TCPR2 : Input capture register 2 (only in channel 2)
Figure 15.1 Block Diagram of TMU
15.2 Input/Output Pins
Table 15.1 shows the TMU pin configuration.
Table 15.1 Pin Configuration
Pin Name
Clock input
Abbreviation
TCLK
I/O
Input
Function
External clock input pin/input capture
control input pin
Rev. 1.0, 02/03, page 510 of 1294