 English |
|
|
|
|
|
|
|
| SH7760 Datasheet, PDF (1259/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine | |||
| |||
| ◁ |
CKIO
A25-A0
CSn
RD/WR
RD
D31-D0
(read)
WEn
D31-D0
(write)
BS
T1
T2
tAD
tCSD
tRWD
tAD
tCSD
tRWD
tRSD
tRSD
tRSD
tRDS
tRDH
tWED1
tWEDF
tWEDF
tWDD
tWDD
tWDD
tBSD
tBSD
RDY
DACKn
(SA: IO memory)
DACKn
(SA: IO memory)
DACKn
(DA)
tDACD
tDACDF
tDACD
tDACD
tDACD
tDACDF
tDACD
Notes: IO : Dack device
SA : Single address DMA transfer
DA : Dual address DMA transfer
DACK set to active-high
Figure 33.17 SRAM Bus Cycle: Basic Bus Cycle (No Wait)
Rev. 1.0, 02/03, page 1209 of 1294
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese