SH7760 Datasheet, PDF (1025/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Initial
Bit Name Value R/W Description
1
BYTE1 0
0
BYTE0 0
R/W*
R/W*
Specifies byte position for on-chip register.
Specifies which 8 or 16 bits of the 32-bit register are to
be accessed.
• MFISCR.BO = 0
8-bit bus
16-bit bus
00: Register bits 31 to 24
01: Register bits 23 to 16
10: Register bits 15 to 8
11: Register bits 7 to 0
Register bits 31 to 16
Setting prohibited
Register bits 15 to 0
Setting prohibited
• MFISCR.BO = 1
8-bit bus
16-bit bus
00: Register bits 7 to 0
01: Register bits 15 to 8
10: Register bits 23 to 16
11: Register bits 31 to 24
Register bits 15 to 0
Setting prohibited
Register bits 31 to 16
Setting prohibited
However, with MFIDATA selected by bits REG5 to
REG0, each time reading from or writing to MFIDATA
from the external device occurs, bits BYTE1 and BYTE0
change according to the following rules.
8-bit bus: 00 Æ 01 Æ 10 Æ 11 Æ 00 Æ 01... etc.
16-bit bus: 00 Æ 10 Æ 00 Æ 10... etc.
Note: * The external device can write to these bits via the MFI only when the MFI-RS pin is 1. The
on-chip CPU cannot write to these bits.
27.3.2 MFI General Status Register (MFIGSR)
The MFIGSR is a 32-bit register which an MFI-connected external device uses to indicate its
status to the on-chip CPU and vice versa. When the MFI-RS pin is driven high, this register is
read-only via the MFI. To write to the MFIGSR from the MFI, specify MFIGSR setting bits
REG5 to REG0, drive the MFI-RS pin low and then perform writing. In this state, the MFIGSR
can also be read.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
- ^{STA STA STA STA STA STA STA STA}
TUS7 TUS6 TUS5 TUS4 TUS3 TUS2 TUS1 TUS0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.0, 02/03, page 975 of 1294