SH7760 Datasheet, PDF (615/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name Initial Value R/W Description
2
PER
0
R
Parity Error
In asynchronous mode, indicates whether or not
a parity error has been found in the data that is to
be read next from SCFRDR.
0: There is no parity error that is to be read from
SCFRDR
[Clearing conditions]
• Power-on reset or manual reset
• When there is no parity error in the data that
is to be read next from SCFRDR
1: There is a parity error in the receive data that
is to be read from SCFRDR
[Setting condition]
1
RDF
0
R/W*¹
• When there is a parity error in the data that is
to be read next from SCFRDR
Receive FIFO Data Full
Indicates that the received data has been
transferred from SCRSR to SCFRDR, and the
number of receive data bytes in SCFRDR is
equal to or greater than the receive trigger
number set by bits RTRG1 and RTRG0 in
SCFCR.
0: The number of receive data bytes in SCFRDR
is less than the receive trigger set number
[Clearing conditions]
• Power-on reset or manual reset
• When SCFRDR is read until the number of
receive data bytes in SCFRDR falls below the
receive trigger set number after reading RDF
= 1, and 0 is written to RDF
• When SCFRDR is read by the DMAC until the
number of receive data bytes in SCFRDR
falls below the receive trigger set number
1: The number of receive data bytes in SCFRDR
is equal to or greater than the receive trigger
set number
[Setting condition]
• When SCFRDR contains at least the receive
trigger set number of receive data bytes*³
Rev. 1.0, 02/03, page 565 of 1294