SH7760 Datasheet, PDF (1107/1345 Pages) Renesas Technology Corp – SuperHTM RISC engine

Bit
Bit Name
12
VINTSEL
11 to 9 
8
VINTE
7 to 1 
0
VINTS
Initial Value R/W
0
R/W
All 0
R
0
R/W
All 0
R
0
R/W
Description
Vsync Interrupt Select
Sets the starting point of the LCDC's Vsync
interrupt.
0: Vsync interrupt occurs at the beginning of access
to synchronous DRAM
1: Vsync interrupt occurs at the beginning of the
LCD display vertical retrace period
Reserved
These bits are always read as 0. The write value
should always be 0.
Vsync Interrupt Enable
Sets whether or not to generate LCDC's Vsync
interrupts.
0: Vsync interrupts are disabled
1: Vsync interrupts are enabled
Reserved
These bits are always read as 0. The write value
should always be 0.
Vsync Interrupt State
Indicates the LCDC's Vsync interrupt handling
state. This bit is set to 1 at the time a Vsync
interrupt is generated. During the processing
routine for Vsync interrupt, clear the register by
entering a value of 0.
0: LCDC did not generate a Vsync interrupt or has
been informed that the generated Vsync
interrupt has completed
1: LCDC has generated a Vsync interrupt and has
not yet been informed that the generated Vsync
interrupt has completed
When Vsync interrupts are enabled, the VINTE bit
must be set to 1 before the DON bit is set to 1, and
the VINTE bit must not be cleared to 0.
When the VINTE bit is set to 0, Vsync interrupts are
not generated.
Rev. 1.0, 02/03, page 1057 of 1294