PXR40RM Datasheet, PDF (988/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
27.3.1 Normal Mode
This is the default operational mode when the EQADC is not in streaming mode or background debug or
stop mode.
27.3.2 Streaming Mode
This mode is characterized by two main aspects: the abort action by CFIFO0 in any current conversion
process started from another queue, and the loop behavior of the CFIFO0.
In some applications, there may be sequences of identical commands each spaced only by a few
microseconds. To reduce the DMA data transfer, in this mode a short command queue can be stored in
CFIFO0 and repeatedly be executed based on a timed trigger, but advance to the next (repeating) sequence
of commands based on another device’s internal trigger.
The CFIFO0 delivers commands to the ADC as before, but those commands are not ‘invalidated’ after they
are sent (in fact, they are ‘invalidated’ only because the Transfer Next Data Pointer has moved on). When
it encounters these repeated commands the CFIFO0 only fills once, using the DMA as usual, until either
it is full or a command with End-of-Queue is encountered. Thereafter the sub-queue repeats/wraps. The
number of commands loaded is unaffected by the delivery of commands once the streaming mode is
configured, since no commands loaded are invalidated even if sent before all the queue is loaded.
The number of entries in the CFIFO0 is extended to eight (configurable). This is to facilitate the targeted
applications. The repeating subqueue must be contained within the eight CFIFO0 entries.
To maintain compatibility, CFIFO0 by default operates as it does before, without streaming and with four
entries. Streaming, and additional entries, can be enabled independently.
Streaming mode is selected as another mode for queue 0 using the configuration bits in the
EQADC_CFCR register. Streaming mode makes use of an additional bit in the Conversion Command
Word (CCW); this bit is called ‘Repeat’. The purpose of this bit is to mark in the command queue, where
to start a repeating sequence.
Streaming mode requires 2 trigger inputs. The standard queue 0 trigger, in this mode referred to as ‘Repeat
Trigger’ and a second internal trigger input to the eQADC called ‘Advance’ trigger.
27.3.3 Debug Mode
Upon a debug mode entry request, EQADC behavior will vary according to the status of the DBG field in
the EQADC_MCR. If DBG is programmed to 0b00, the debug mode entry request is ignored. If DBG is
programmed to 0b10 or to 0b11, the EQADC will enter debug mode.
During debug mode, the EQADC will not transfer commands from any CFIFOs, no data will be returned
to any RFIFO, no hardware trigger event will be captured, and all EQADC registers can be accessed as in
Normal mode. The latter implies that CFIFOs can still be triggered using software triggers, since no
scheme is implemented to write-protect registers during debug mode. DMA and interrupt requests
continue to be generated as in Normal Mode.
If at the time the debug mode entry request is detected, there are commands in the on-chip CBuffers that
were already under execution, these commands will be completed but the generated results, if any, will not
27-6
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor