PXR40RM Datasheet, PDF (253/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Table 7-46. SIU_HLT Register Field Descriptions
Field
Description
0-31
HLT
Halt Selects
The HLT bits halt specific modules. Each bit corresponds to a separate module as
mapped below:
0 CPU and platform¹
1 rsvd
2 rsvd
3 rsvd
4 rsvd
5 eTPU_A and eTPU_B
6 NPC
7 EBI
8 eQADCs: eQADC_A and eQADC_B
9 rsvd
10 eMIOS_A
11 DECFILTs (decimation filters)
12 rsvd
13 PIT
14 rsvd
15 rsvd
16FlexCAN_D
17 FlexCAN_C
18 FlexCAN_B
19 FlexCAN_A
20 DSPI_D
21 DSPI_C
22 DSPI_B
23 DSPI_A
24 rsvd
25 rsvd
26 rsvd
27 rsvd
28 rsvd
29 eSCI_C
30 eSCI_B
31 eSCI_A
1 _{Stops all CPU clocks; stops the platform, excluding interrupt controller and watchdogs. Note:}
these are only halted when the CPU executes a wait instruction to request the halt.
7.3.1.29 Halt Acknowledge Register (SIU_HLTACK)
The SIU_HLTACK bits indicate that the module requested to halt via the HLT bit has completed the halt
process and has entered a halted state with the module clocks disabled. The HLTACK bits are read-only
and writes have no effect, it is reset by the internal reset condition. The input signals from each module
will be connected as shown in Table 7-47., HALT Acknowledge Register Field Descriptions.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-71