PXR40RM Datasheet, PDF (117/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Signal Descriptions
Table 3-13. EBI Signals (Development Bus Only) (continued)
Signal Name
D_RD_WR_GPIO294
D_WE0_GPIO295
D_WE1_GPIO296
D_OE_GPIO297
D_TS_GPIO298
D_ALE_GPIO299
D_TA_GPIO300
D_CS1_GPIO301
D_BDIP_GPIO302
D_WE2_GPIO303
D_WE3_GPIO304
D_ADD9_GPIO305
D_ADD10_GPIO306
D_ADD11_GPIO307
Description
Indicates whether an external bus transfer is a read or write operation.
Write/Byte enable specify which data pins contain valid data for an external bus transfer.
Output enable indicates that the EBI is ready to accept read data.
Transfer start is asserted by the EBI owner to indicate the start of a transfer.
Address latch enable is used to demultiplex the address from data bus. It is asserted while
the least significant 16 bits of the address are present in the multiplexed address/data bus.
Transfer acknowledge is asserted by the EBI owner to acknowledge that the slave has
completed the current transfer.
EBI chip select output signal.
Burst Data In Progress indicates that an EBI burst transfer is in progress.
Write/Byte enable specify which data pins contain valid data for an external bus transfer.
EBI address signals.
3.3.10 Reset and Clock Signals
Table 3-14. Reset and Clock Signals
Signal Name
RESET
RSTOUT
BOOTCFG[0:1]_IRQ[2:3]_
GPIO[211:212]
WKPCFG_NMI_GPIO213
PLLCFG0_IRQ4_GPIO208
PLLCFG1_IRQ5_GPIO209
PLLCFG2
Description
The RESET input is asserted by an external device to reset the all modules of the device
MCU. The RESET pin must be asserted during a power-on reset.
The RSTOUT output is a push/pull output that is asserted during an internal device reset.
The pin can also be asserted by software without causing an internal reset of the device
MCU.
Note: During a power-on-reset (POR), RSTOUT is tri-stated.
BOOTCFG[0:1] signals are sampled on every reset. The values are used by the Boot
Assist Module (BAM) program to determine the boot configuration of the device. The
alternate functions are the external interrupt request inputs (IRQs).
WKPCFG (sampled at every reset) determines whether specific eTPU and eMIOS pins
are connected to a weak pullup or weak pulldown during and immediately after reset. The
alternate function (NMI) is a critical interrupt to the core.
PLLCFGn are sampled at every reset. These values are used to configure the FMPLL
mode of operation. The alternate function is an external interrupt request input.
PLLCFGn are sampled at every reset. These values are used to configure the FMPLL
operation mode. The alternate functions are an external interrupt request input and data
output for the DSPI module D.
PLLCFGn are sampled at every reset. These values are used to configure the FMPLL
operation mode. PLLCFG2 configures the crystal oscillator range.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
3-51