PXR40RM Datasheet, PDF (879/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Address: DSPI_BASE + 0x2C
Access: R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
TXRXS 0
0
0
0
0
0
0
0
0
TCF
EOQF TFUF
TFFF
RFOF
RFDF
W
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
16
R
W
Reset 0
17
18 19
20 21 22 23 24 25
26
27
TXCTR
TXNXTPTR
RXCTR
0 0 0 0 0 0 00 0 0 0
Figure 25-6. DSPI Status Register (DSPI_SR)
28
29
30
31
POPNXTPTR
0000
Table 25-14. DSPI_SR Field Descriptions
Field
0
TCF
1
TXRXS
2
3
EOQF
4
TFUF
5
6
TFFF
7–11
Description
Transfer Complete Flag. The TCF bit indicates that all bits in a frame have been shifted out. The TCF
bit is set at the end of the frame transfer. The TCF bit remains set until cleared by software.
0 Transfer not complete
1 Transfer complete
TX & RX Status. The TXRXS bit reflects the status of the DSPI. See Section 25.4.2, Start and Stop
of DSPI Transfers, for information on how what causes this bit to be negated or asserted.
0 TX and RX operations are disabled (DSPI is in STOPPED state)
1 TX and RX operations are enabled (DSPI is in RUNNING state)
Reserved, should be cleared.
End of Queue Flag. The EOQF bit indicates that transmission in progress is the last entry in a queue.
The EOQF bit is set when TX FIFO entry has the EOQ bit set in the command halfword and the end
of the transfer is reached. The EOQF bit remains set until cleared by software. When the EOQF bit is
set, the TXRXS bit is automatically cleared.
0 EOQ is not set in the executing command
1 EOQ bit is set in the executing SPI command
Transmit FIFO Underflow Flag. The TFUF bit indicates that an underflow condition in the TX FIFO has
occurred. The transmit underflow condition is detected only for DSPI blocks operating in slave mode
and SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode
is empty, and a transfer is initiated by an external SPI master. The TFUF bit remains set until cleared
by software.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
Reserved, should be cleared.
Transmit FIFO Fill Flag. The TFFF bit provides a method for the DSPI to request more entries to be
added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be cleared
by host software or an acknowledgement from the DMA controller when the TX FIFO is full.
0 TX FIFO is full
1 TX FIFO is not full
Reserved, should be cleared.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-19