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PXR40RM Datasheet, PDF (839/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller
FlexCAN Module
Table 24-14. FLEXCAN_x_IMASK1 Field Descriptions
Field
Description
0–31 Buffer MBi Mask
BUF31M Each bit enables or disables the respective FlexCAN Message Buffer (MB0 to MB31) Interrupt.
–BUF0M 0 The corresponding buffer Interrupt is disabled
1 The corresponding buffer Interrupt is enabled
Note: Setting or clearing a bit in the FLEXCAN_x_IMASK1 Register can assert or negate an interrupt request, if the
corresponding FLEXCAN_x_IFLAG1 bit is set.
24.3.4.11 Interrupt Flags 2 Register (FLEXCAN_x_IFLAG2)
This register defines the flags for 32 Message Buffer interrupts. It contains one interrupt flag bit per buffer.
Each successful transmission or reception sets the corresponding FLEXCAN_x_IFLAG2 bit. If the
corresponding FLEXCAN_x_IMASK2 bit is set, an interrupt will be generated. The interrupt flag must be
cleared by writing it to ‘1’. Writing ‘0’ has no effect.
When the AEN bit in the FLEXCAN_x_MCR is set (Abort enabled), while the FLEXCAN_x_IFLAG2
bit is set for a MB configured as Tx, the writing access done by CPU into the corresponding MB will be
blocked.
Base + 0x002C
R
W
RESET:
0
BUF
63I
0
1
BUF
62I
0
2
BUF
61I
0
3
BUF
60I
0
4
BUF
59I
0
5
BUF
58I
0
6
BUF
57I
0
7
BUF
56I
0
8
BUF
55I
0
9
BUF
54I
0
10
BUF
53I
0
11
BUF
52I
0
12
BUF
51I
0
13
BUF
50I
0
14
BUF
49I
0
15
BUF
48I
0
R
W
RESET:
16
BUF
47I
0
17
BUF
46I
0
18
BUF
45I
0
19
BUF
44I
0
20
BUF
43I
0
21
BUF
42I
0
22
BUF
41I
0
23
BUF
40I
0
24
BUF
39I
0
25
BUF
38I
0
26
BUF
37I
0
27
BUF
36I
0
28
BUF
35I
0
29
BUF
34I
0
30
BUF
33I
0
31
BUF
32I
0
Figure 24-13. Interrupt Flags 2 Register (FLEXCAN_x_IFLAG2)
Table 24-15. FLEXCAN_x_IFLAG2 Field Descriptions
Field
Description
0–31 Buffer MBi Interrupt
BUF32I– Each bit flags the respective FlexCAN Message Buffer (MB32 to MB63) interrupt.
BUF63I 0 No such occurrence
1 The corresponding buffer has successfully completed transmission or reception
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
24-29