PXR40RM Datasheet, PDF (929/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 26 Enhanced Serial Communication Interface
(eSCI)
26.1 Introduction
The eSCI block is an enhanced SCI block with a LIN master interface layer and DMA support. The LIN
master layer complies with the specifications LIN 1.3, LIN 2.0, LIN 2.1, and SAE J2602/1.
26.1.1 Bibliography
• LIN Specification Package Revision 1.3; December 12, 2002
• LIN Specification Package Revision 2.0; September 23, 2003
• LIN Network for Vehicle Applications, SAE J2602/1, September 1, 2005
• LIN Specification Package Revision 2.1; November 24, 2006
26.1.2 Acronyms and Abbreviations
Table 26-1 contains acronyms and abbreviations used in this document.
Table 26-1. Acronyms and Abbreviations
Term
Description
eSCI
SCI
LIN
LIN PE
MCLK
TCLK
RCLK
RSC
Enhanced SCI block with LIN support and DMA support
Serial Communications Interface
Local Interconnect Network - A protocol for low-cost automobile networks
LIN Protocol Engine, Finite State Machine to control logic of the LIN hardware.
Module Clock, defined in Section 26.4.3.1, Module Clock
Transmitter Clock, defined in Section 26.4.3.2, Transmitter Clock
Receiver Clock, defined in Section 26.4.3.3, Receiver Clock
Receiver Sample Counter, defined in Section 26.4.3.3, Receiver Clock
26.1.3 Glossary
Table 26-2. Glossary
Term
Definition
Logic level one The voltage that corresponds to Boolean true (1) state.
Logic level zero The voltage that corresponds to Boolean false (0) state.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-1