PXR40RM Datasheet, PDF (1171/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
Shared Data Memory - SDM - holds eTPU application parameters and work data. It is accessed by Host
and both microengines.
Bus Interface Unit - BIU - allows Host to access eTPU registers, SCM and SDM.
Each I/O signal pair is associated with a dedicated Channel, which provides hardware for input signal
processing and output signal generation, in relationship with selected Time Bases.
The eTPU, as a microprocessed subsystem, works much like a typical real-time system: it runs
microengine code from instruction memory (SCM) to handle specific events, accessing data memory
(SDM) for parameters, work data and application state info; events may originate from I/O Channels (due
to pin transitions and/or time base matches), Host CPU requests or inter-channel requests; events that call
for local eTPU processing activate the microengine by issuing a Service Request. The Service Request
microcode may set an interrupt to the Host CPU. I/O channel events cannot directly interrupt the Host
CPU.
Each Channel is associated with a Function, which defines its behavior: the Function is a software entity
consisting, within the eTPU, of a set of microengine routines that attend to Service Requests. The Function
routines are also responsible for Channel configuration. Function routines reside in SCM, which may
contain several Functions. A Function may be assigned to several Channels, but a Channel can be
associated with just one Function at a given moment. The association between Functions and Channels is
defined by Host CPU, and is explained in detail in the eTPU Reference Manual.
eTPU hardware supplies resource sharing features that support concurrency:
• a hardware Scheduler dispatches the Service Request microengine routines based on a set of
priorities defined by the Host CPU. Each Channel has its associated priority;
• a Service Request routine cannot be interrupted until it ends. This sequence of uninterrupted
instruction execution is called a Thread.
• Channel-specific context (registers and flags) is automatically switched between the end of a
Thread and the beginning of the next one.
• SDM arbitration, a dual-parameter coherency controller and semaphores can be used to ensure
coherent access to eTPU data shared by both eTPU Engines and Host CPU.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-3