PXR40RM Datasheet, PDF (1016/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Field
0–15
16–19
24–27
REDBSm
Table 27-16. EQADC_REDLCCR Field Descriptions
Description
Reserved
Red Line Timebase Bits Selection m (m=1,2)—Selects 16 bits from the total of 24 bits that are received
from the Red Line interface as described in below. Consider TBASEm[0:23] the selected time base from
slot SRVm:
REDBSm[0:3]
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
Others
Selected Bits
TBASEm[0:15]
TBASEm[1:16]
TBASEm[2:17]
TBASEm[3:18]
TBASEm[4:19]
TBASEm[5:20]
TBASEm[6:21]
TBASEm[7:22]
TBASEm[8:23]
Reserved
20–23
28–31
SRVm
Red Line Server Data Slot Selector m (m=1,2)—Indicates the slot number that contains the desired time
base value sent by the Red Line server. This value selects which eTPU timebase on the STAC bus is used
to timestamp an ADC sample.
SRVm[0:3]
0b0000
0b0001
0b0010
0b0011
0b0100 - 0b1111
eTPU Timebase
eTPUA TCR1
eTPUB TCR1
eTPUA TCR2
eTPUB TCR2
Reserved
27.6.2.12 EQADC CFIFO Registers (EQADC_CFxRw) (x=0, ..,5; w=0, .., 3)
The EQADC CFIFO Registers (EQADC_CFxRw) (x=0, .., 5; w=0, .., 3) provide visibility of the contents
of a CFIFO for debugging purposes. Each CFIFO has four registers which are uniquely mapped to its four
32-bit entries. Refer to Section 27.7.4, EQADC Command FIFOs, for more information on CFIFOs. These
registers are read only. Data written to these registers is ignored.
27-34
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor