PXR40RM Datasheet, PDF (969/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
RXD
left shifted falling edge
sample counter reset
DATA FALLING
VOTING EDGE
DATABIT N-1
DATA
VOTING
DATABIT N
DATA
VOTING
DATABIT N+1
RCLK
RSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5
wrap
reset
Figure 26-35. Data Bit Synchronization (Left Shifted Edges)
If the 0-sample of the falling edge condition is received at sample 9 or 10, no sample counter
synchronization is performed.
26.4.5.3.18 Stop Bit Verification
The reception of a valid stop bit is verified if at least two out of the sample RS8, RS9, and RS10 are
sampled high. If this is not that case, a framing error is detected. Noise is detected if not all of the samples
are of the same value. The results of the stop bit verification are summarized in Table 26-35.
Table 26-35. Stop Bit Verification
[RS8, RS9, RS10]
000
001
010
100
011
101
110
111
Stop Bit Verified
No
No
No
No
Yes
Yes
Yes
Yes
Framing Error Detected
Yes
Yes
Yes
Yes
No
No
No
No
Noise Detected
No
Yes
Yes
Yes
Yes
Yes
Yes
No
26.4.5.3.19 Parity Checking
The eSCI module calculates the parity of a received character and checks is versus the received parity bit
in the received data frame when the parity enable bit PE in the Control Register 1 (eSCI_CR1) is set. The
parity type bit PT in the Control Register 1 (eSCI_CR1) defines whether to check for odd or even parity is
generated. If an parity error is detected, this is reported as described in Section 26.4.5.4, Reception Error
Reporting.
26.4.5.4 Reception Error Reporting
The receiver can detect four error types: parity errors, framing errors, noise errors, and the overrun error.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-41