PXR40RM Datasheet, PDF (1059/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
EQADC
ADC0
CBuffer0
(2 entries)
Abort
Prioritization Logic
Cont0
Command
Prioritization
for CBuffer0
Usage
Command
CFIFO0
Command _CFIFO1
ADC1
CBuffer1
(2 entries)
Abort
Cont1
Command
Prioritization
for CBuffer1
Usage
6 x Command
Command _CFIFO2
Command _CFIFO3
Command _CFIFO4
Command _CFIFO5
Figure 27-54. CFIFO Prioritization Logic
27.7.4.4 CFIFO Prioritization in Abort Mode
The CFIFO priority does not change when the EQADC is configured to allow abortion of conversion
execution in on-chip ADC analog blocks. However, CFIFO0 is the only one that can be enabled to abort
conversions.
This feature is necessary when the timing of some conversion is very important. In normal priority scheme,
when CFIFO0 is triggered, its conversion command can be put behind 2 pending conversion commands
in the Cbuffer due to the queue structure. Considering that these 2 pending commands are from lower
priority CFIFOs and that the delay between the trigger and the sampling of the command from Cqueue0
can be unacceptable, EQADC can be configured to permit immediate conversion commands from CFIFO0
with abort function.
When CFIFO0 is triggered and abort is enabled, up to 2 commands in Cbuffer0 or Cbuffer1 are stored in
a side register. The abort request signal is generated to ADC0 or ADC1 and the confirmation of ADC
reset/ready is waited to send the command from CFIFO0 to the decoded Cbuffer.
After the transfer of all commands from CFIFO0, the recovery phase restores the up to 2 commands that
were in Cbuffer when the abort occurred. After this recovery phase, it is established the normal process of
prioritization of commands from CFIFOs.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-77