PXR40RM Datasheet, PDF (221/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Address
Offset
GPIO
Primary
Function
Table 7-22. SIU_PCRn Settings (continued)
SIU_PCRn[3:15]¹
(SIU_PCRn[0:2] = Reserved, should be cleared)
A2
A3
A4 _{3 4 5 6 7 8 9 10 11 12 13 14 15}
465 0x03E2 GPIO465 —
PCSD4
MAA1
MAB1 0 0 0 0 0 — — 0 0 0 0 1 U
466 0x03E4 GPIO466 —
PCSD3
MAA2
MAB2 0 0 0 0 0 — — 0 0 0 0 1 U
467 0x03E6 GPIO467 —
PCSD2
—
—
— 0 0 0 0 —— 0 0 0 0 1 U
468 0x03E8
469 0x03EA
470 0x03EC
GPIO468 —
GPIO469 —
GPIO470 —
PCSD1
—
—
— 0 0 0 0 —— 0 0 0 0 1 U
PCSD0⁴
—
—
— 0 0 0 0 —— 0 0 0 0 1 U
SCKD⁴
—
—
— 0 0 0 0 —— 0 0 0 0 1 U
471 0x03EE GPIO471 —
SOUTD
—
—
— 0 0 0 0 —— 0 0 0 0 1 U
472 0X03F0 GPIO472 —
SIND⁴
—
—
— 0 0 0 0 —— 0 0 0 0 1 U
1 _{“—” means the field is not implemented in the PCR (and a default value of 0 should be written)}
“U” means the field is defined by the WKPCFG pin at reset
2 _{PCR75–PCR82: reduced port mode MDO pins, only DSC bits should be driven by PCR (also IBE and OBE for GPIO).}
3 _{GPIO functionality available on Rev.2 of the device.}
4 _{Selection of this function may be affected by a higher priority PCR. See Table 7-21.}
5 _{When the SIU_ISEL8 register is in its default state, this eTPU pin will not be enabled as an input, irrespective of the SIU_PCR[PA] field.}
6 _{PCR231–PCR234: PA are controlled by Nexus Port Controller (NPC). The Full Port Mode (FPM) bit in the NPC pad configuration register controls}
whether the pins function as MDO or GPIO. The pad interface port enable is driven by the NPC block. When the FPM bit is set, the NPC enables
the MDO port enable, and disables GPIO. When the FPM bit is cleared, the NPC disables the MDO port enable, and enables GPIO.
– The OBE bit applies only to GPIO operation
– Clear the ODE bit to 0 for MDO operation
– The HYS bit has no effect on MDO operation
– Clear the WPE bit to 0 for MDO operation
7 _{Bit = 1 only for Rev.2 of the device.}