PXR40RM Datasheet, PDF (1119/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
28.1.2.2 Freeze Mode
This mode is also known as debug mode. All filter action is frozen. If the filter is processing an input, it
enters freeze mode only after the current processing finishes. More details of freeze mode may be found
in Section 28.3.8, Freeze Mode.
28.1.2.3 Disabled Mode
Each Decimation Filter block may be disabled by setting the DECFILT_x_MCR[MDIS] bit in the
respective block instance.
28.2 Memory Map and Register Definition
This section provides the memory maps and detailed descriptions of all registers. There are eight
Decimation Filter blocks on the device. Each Decimation Filter block has its own independent set of
registers as defined in Section 28.2.2, Decimation Filter Register Descriptions. The base address of each
Decimation Filter block is given in Table 28-2.
Table 28-2. Decimation Filter Modules Base Address
Module
DECFILT_A_ BASE
DECFILT_B_ BASE
DECFILT_C_ BASE
DECFILT_D_ BASE
DECFILT_E_ BASE
DECFILT_F_ BASE
DECFILT_G_ BASE
DECFILT_H_ BASE
Address
0xFFF8_8000
0xFFF8_8800
0xFFF8_9000
0xFFF8_9800
0xFFF8_A000
0xFFF8_A800
0xFFF8_B000
0xFFF8_B800
28.2.1 Decimation Filter Memory Map
The addresses of the Decimation Filter registers are specified as offsets from the module’s base address as
described in Table 28-3.
Table 28-3. Block Memory Map
Address
Register
DECFILT_x_ BASE + DECFILTER_MCR — Module Configuration
0x000
Register
DECFILT_x_ BASE + DECFILTER_MSR — Module Status Register
0x004
DECFILT_x_ BASE + DECFILTER_MXCR — Module Extended
0x008
Configuration Register
Bits Access Reset Value Section/Page
32 R/W 0x0000_0000 28.2.2.1/28-7
32 R/W 0x0000_0000 28.2.2.2/28-11
32 R/W 0x0000_0000 28.2.2.3/28-13
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-5