PXR40RM Datasheet, PDF (412/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Field
Description
Data Address Space
27
DS
0 - The processor directs all data storage accesses to address space 0 (TS=0 in the
relevant TLB entry).
1 - The processor directs all data storage accesses to address space 1 (TS=1 in the
relevant TLB entry).
28
Reserved¹
29
PMM
PMM Performance monitor mark bit.
System software can set PMM when a marked process is running to enable statistics
to be gathered only during the execution of the marked process. MSR_PR and
MSR_PMM together define a state that the processor (supervisor or user) and the
process (marked or unmarked) may be in at any time. If this state matches an
individual state specified in the Performance Monitor registers PMLCa n, the state
for which monitoring is enabled, counting is enabled.
30
Recoverable Interrupt - This bit is provided for software use to detect nested exception
RI
conditions. This bit is cleared by hardware when a Machine Check interrupt is taken
31
Reserved¹
1 _{These bits are not implemented, will be read as zero, and writes are ignored.}
13.6.1 Machine Check Syndrome Register (MCSR)
When the processor takes a machine check interrupt, it updates the Machine Check Syndrome register
(MCSR) to differentiate between machine check conditions.
0
0
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 572; Read/Clear; Reset - 0x0
Figure 13-14. Machine Check Syndrome Register (MCSR)
Table below describes MCSR fields. The MCSR indicates the source of a machine check condition.
All bits in the MCSR are implemented as “write ‘1’ to clear”. Software in the machine check handler is
expected to clear the MCSR bits it has sampled prior to re-enabling MSR_ME to avoid a redundant machine
check exception and to prepare for updated status bit information on the next machine check interrupt.
Hardware will not clear a bit in the MCSR other than at reset.
Note that any set bit in the MCSR other than status-type bits will cause a subsequent machine check
interrupt once MSR_ME=1.
13-24
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor