PXR40RM Datasheet, PDF (1223/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.3.2.7 Bus Error Conditions
Follows a summary of the possible causes of bus errors on host accesses to the eTPU memory space:
• Read or write access to the SCM with ETPUMCR bit VIS=0.
• Read or write access to the channel registers with ETPUECR bits MDIS=1, or bit STF=1.
• Write access to the Time Base Registers with ETPUECR bits MDIS=1, or bit STF=1.
• Non-correctable errors in the SCM on reads of any size or writes less than 32-bits wide, when
ETPUMECR bit CEDD=0.
• Non-correctable errors in the SDM on reads, when ETPUMECR bit DEDD=0.
29.3.3 Scheduler
Every Function is composed of one or more Threads. A Thread consists of a group of instructions that,
once begins execution, cannot be interrupted by host or channel events. Each active channel intents to be
serviced, being granted time for Thread execution. Since one microengine handles several channels
operating concurrently, the Function threads must be executed serially.
The task of the Scheduler is to recognize and prioritize the channels needing service and to grant execution
time to each channel. The time given to an individual Thread for execution or service is called a Time Slot.
The duration of a time slot is determined by the number of instructions executed in the Thread plus SDM
wait-states received, and varies in length.
At any time, an arbitrary number of channels can require service. To request service, channel logic, eTPU
microcode or Host application notifies the Scheduler by issuing a Service Request.
29.3.3.1 Channel Enabling and Priority Assignment
Every channel is assigned one of three priority levels - high, middle, or low - by the Host CPU, through
the Channel Configuration Register field CPR (see Section 29.2.10.1, ETPUCxCR - eTPU Channel x
Configuration Register). These registers are also used to disable the channel, which is equivalent to
assigning it a “null” priority. In this case, the Scheduler does not grant any of its Service Requests.
It is possible to change the channel priority level or disable it dynamically. If the Host disables a channel
when it is currently being serviced, channel service thread will complete. This means that it is possible for
the output level of a channel signal to change, or a Host interrupt occur, even after its priority register was
written to “null”. For instance, if an output transition is scheduled, the transition will occur even after the
channel is disabled.
Service requests previously pending or that occur while a channel is disabled remain asserted while the
channel is disabled, and are serviced if the channel is enabled again, in due time determined by the priority
scheme and concurrent requests from other channels. Channels are disabled after reset, and it is
recommended to configure a Host Service Request for initialization of a channel before that channel is
enabled to active priority (see Section 29.4, Initialization/Application Information).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-55