PXR40RM Datasheet, PDF (910/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
SCK (CPOL = 0)
SCK (CPOL = 1)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Master and Slave
Sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
PCSx/SS
t_CSC
MSB first (LSBFE = 0): MSB Bit 6 Bit 5 Bit 4
LSB first (LSBFE = 1): LSB Bit 1 Bit 2 Bit 3
t_CSC = PCS to SCK delay
t_ASC = After SCK delay
t_DT = Delay after Transfer (Minimum CS idle time)
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
t_ASC t_{DT tCSC}
Figure 25-29. DSPI Transfer Timing Diagram (MTFE=0, CPHA=0, FMSZ=8)
The master initiates the transfer by placing its first data bit on the SOUT pin and asserting the appropriate
peripheral chip select signals to the slave device. The slave responds by placing its first data bit on its
SOUT pin. After the t_CSC delay has elapsed, the master outputs the first edge of SCK. This is the edge used
by the master and slave devices to sample the first input data bit on their serial data input signals. At the
second edge of the SCK the master and slave devices place their second data bit on their serial data output
signals. For the rest of the frame the master and the slave sample their SIN pins on the odd-numbered clock
edges and changes the data on their SOUT pins on the even-numbered clock edges. After the last clock
edge occurs a delay of t_ASC is inserted before the master negates the PCS signals. A delay of t_DT is inserted
before a new frame transfer can be initiated by the master.
25.4.7.2 Classic SPI Transfer Format (CPHA = 1)
This transfer format shown in Figure 25-30 is used to communicate with peripheral SPI slave devices that
require the first SCK edge before the first data bit becomes available on the slave SOUT pin. In this format
the master and slave devices change the data on their SOUT pins on the odd-numbered SCK edges and
sample the data on their SIN pins on the even-numbered SCK edges
25-50
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor