PXR40RM Datasheet, PDF (595/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Offset
0x00F0
...
0x00FE
0x0100
0x0102
0x0104
0x0106
...
0x04F8
0x04FA
0x04FC
0x04FE
FlexRay Communication Controller (FLEXRAY)
Table 22-3. FlexRay Memory Map (continued)
Register
Access
Reserved
R
Message Buffers Configuration, Control, Status
Message Buffer Configuration, Control, Status Register 0 (MBCCSR0)
R/W
Message Buffer Cycle Counter Filter Register 0 (MBCCFR0)
R/W
Message Buffer Frame ID Register 0 (MBFIDR0)
R/W
Message Buffer Index Register 0 (MBIDXR0)
R/W
...
...
Message Buffer Configuration, Control, Status Register 127 (MBCCSR127)
R/W
Message Buffer Cycle Counter Filter Register 127 (MBCCFR127)
R/W
Message Buffer Frame ID Register 127 (MBFIDR127)
R/W
Message Buffer Index Register 127 (MBIDXR127)
R/W
22.5.2 Register Descriptions
This section provides detailed descriptions of all registers in ascending address order, presented as 16-bit
wide entities
Table 22-4 provides a key for the register figures and register tables.
Table 22-4. Register Access Conventions
Convention
Description
Depending on its placement in the read or write row, indicates that the bit is not readable or not writeable.
R*
Reserved bit or field, will not be changed. Application must not write any value different from the reset value.
FIELDNAME Identifies the field. Its presence in the read or write row indicates that it can be read or written.
Register Field Types
rwm
A read/write bit that may be modified by a hardware in some fashion other than by a reset.
w1c
Write one to clear. A flag bit that can be read, is cleared by writing a one, writing 0 has no effect.
Reset Value
0
Resets to zero.
1
Resets to one.
–
Not defined after reset and not affected by reset.
22.5.2.1 Register Reset
All registers except the Message Buffer Cycle Counter Filter Registers (MBCCFRn), Message Buffer
Frame ID Registers (MBFIDRn), and Message Buffer Index Registers (MBIDXRn) are reset to their reset
value on system reset. The registers mentioned above are located in physical memory blocks and, thus,
they are not affected by reset. For some register fields, additional reset conditions exist. These additional
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-11