PXR40RM Datasheet, PDF (1073/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
CF5_CB1_CM0
CF5_CB1_CM1
CF5_CB1_CM2
CF5_CB1_CM3
CF5_CB1_CM4
CF5_CB1_CM5
CF5_CB1_CM6
CF5_CB1_CM7
CF5_CB1_CM8
CF5_CB1_CM9
CF5_CB1_CM10
CF5_CB1_CM11
CF5_CB1_CM12
CF5_CB1_CM13
Command sequence became non-coherent before command 4
was transferred. Once command transfers are resumed, EQADC
will only check for coherency after command 4.
Command sequence became non-coherent before command 11
was transferred. Once command transfers are resumed, EQADC
will only check for coherency after command 11.
Figure 27-59. Non-coherency Detection when Transfers from a Command Sequence are Interrupted
27.7.5 EQADC Result FIFOs
27.7.5.1 RFIFO Basic Functionality
There are six RFIFOs located in the EQADC. Each RFIFO is four entries deep, and each RFIFO entry is
16 bits long. Each RFIFO serves as a temporary storage location for the one of the RQueues allocated in
system memory. Result data is saved in the RFIFOs before being moved into the system RQueues. When
an RFIFO is not empty, the EQADC sets the corresponding RFDF bit in Section 27.6.2.7, EQADC FIFO
and Interrupt Status Registers (EQADC_FISR). If RFDE is asserted in Section 27.6.2.6, EQADC Interrupt
and DMA Control Registers (EQADC_IDCR), the EQADC generates a request so that an RFIFO entry is
moved to the RQueue. An interrupt request, served by the host CPU, is generated when RFDS is negated,
and a DMA request, served by the DMAC, is generated when RFDS is asserted. The host CPU or the
DMAC responds to these requests by reading Section 27.6.2.4, EQADC Result FIFO Pop Registers
(EQADC_RFPR), to retrieve data from the RFIFO.
NOTE
The DMAC should be configured to read a single result (16-bit data) from
the RFIFO pop registers for every asserted DMA request it acknowledges.
Refer to Section 27.8.2, EQADC/DMAC Interface, for DMAC
configuration guidelines.
NOTE
Reading a word, a half-word, or any bytes from EQADC_RFPRx will pop
an entry from RFIFOx, and the RFCTRx field will be decremented by one.
Figure 27-60 describes the important components in the RFIFO. Each RFIFO is implemented as a circular
set of registers to avoid the need to move all entries at each push/pop operation. The Pop Next Data Pointer
always points to the next RFIFO message to be retrieved from the RFIFO when reading EQADC_RFPR.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-91