PXR40RM Datasheet, PDF (902/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Parallel chaining allows multiple DSPIs internal to a device and multiple SPI/DSI devices external to a
device to share common SCK and PCS signals thereby saving pins. Two pins are saved per pair of
DSPI/SPI. Figure 25-22 shows an example of how the blocks can be connected in a device.
SoC
DSPI Master
SIN
SOUT
PCS[x]
HT
SCK
DSPI Slave
SIN
MTRIG
SOUT
HT
SS
SCK
DSPI Slave
SIN
SOUT
MTRIG
SS
SCK
SS
SOUT
SCK
SIN
SPI Slave Device
SS
SOUT
SCK
SIN
SPI Slave Device
SS
SOUT
SCK
SIN
SPI Slave Device
Figure 25-22. Example of Parallel Chaining of DSPIs
The DSPI master controls and initiates all transfer, but the DSPI slaves have a trigger output signal MTRIG
that indicates to the master DSPI to start a transfer. When the DSPI slave has a change in its data to be
serialized, it generates a pulse on the MTRIG signal to the master DSPI which initiates the transfer. When
a DSPI slave has its HT signal asserted it also generates a pulse on its MTRIG signal thereby propagating
trigger signals from other DSPI slaves to the DSPI master.
The MTOCNT field in the DSPI_DSICR must be written with the number of bits to be transferred. In
parallel chaining the number written to MTOCNT must match the FMSZ field in the selected DSPI_CTAR
register.
25.4.4.6.2 Serial Chaining
The serial chaining allows transfers of DSI frames of up to a total of 64 bits, using transfers of smaller DSI
frames concatenated together by multiple DSPIs. Figure 25-23 shows an example of how the blocks can
be connected in a device.
25-42
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor