PXR40RM Datasheet, PDF (958/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Transition
start
done
halt
Table 26-27. Transmitter Module Transitions
Condition
Action
Description
(State=Ready)
and
(SBK=1 or iPRE=1 or iCMT=1)
TACT:=1
Start of transmission of data frame or special
character when data are available or character
transmission request is pending.
State=Run
and
last stop bit transmitted
TACT:=0
Finished transmission of data frame or special
TC:=
character and transmitter still enabled. Transmission
(SBK & iPRE & TC) is complete if no transmit request is pending.
State=Stop
and
last stop bit transmitted
TACT:=0
TC:=1
iCMT:=0
Finished transmission of data frame or special
character and transmitter was disabled.
26.4.5.2.2 Frame and Character Transmission
The transmitter starts the transmission of a data frame or special character when the condition for the start
transition as described in Table 26-27 is fulfilled. There are three source for data or character transmission.
The priority among these source are specified in Table 26-28. All three sources can be available at one
point in time.
Table 26-28. Transmit Source Priority
Priority
Indication
Transmission Source
(highest) 0
1
(lowest) 2
eSCI_CR1[SBK]=1
iPRE=1
iCMT=1
Break character.
Preamble.
SCI Data Register (ESCI_DR) frame.
26.4.5.2.3 CPU Controlled SCI Data Frame Transmission
The transmission of a data frame is started when the transmitter is in its Ready state and only the commit
bit iCMT is set.
As the first step, the content of the SCI Data Register (ESCI_DR) is transferred into the internal transmitter
shift register. When this transfer is finished, the internal commit bit iCMT is cleared and the transmit data
register empty flag TDRE in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set. If the transmit
interrupt enable bit TIE in the Control Register 1 (eSCI_CR1) is also set, the TDRE flag generates a
transmitter interrupt request.
The transmitter shift register then shifts a frame out through the TXD output signal, which is prefaced with
a start bit and appended with the parity bit, if configured, and the configured number of stop bits.
When the last stop bit has been transmitted and the application has not disabled the transmitter, the
transmitter returns to the Ready state via the done transition. If no frame or character transmit request is
pending, the transfer complete flag TC in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set.
If the application has disabled the transmitter while the frame is transmitted and stop bit has been
transmitted, the transmitter goes into the Idle state via the halt transition. The transfer complete flag TC in
the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit iCMT is cleared.
26-30
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor