PXR40RM Datasheet, PDF (843/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
prioritization of MBs to be transmitted based on the message ID (optionally augmented by 3 local priority
bits) or the MB ordering.
Before proceeding with the functional description, an important concept must be explained. A Message
Buffer is said to be “active” at a given time if it can participate in the matching and arbitration algorithms
that are happening at that time. An Rx MB with a ‘0000’ code is inactive (refer to Table 24-5). Similarly,
a Tx MB with a ‘1000’ or ‘1001’ code is also inactive (refer to Table 24-6). An MB not programmed with
‘0000’, ‘1000’ or ‘1001’ will be temporarily deactivated (will not participate in the current arbitration or
matching run) when the CPU writes to the C/S field of that MB (see Section 24.4.6.2, Message Buffer
Deactivation).
24.4.2 Transmit Process
In order to transmit a CAN frame, the CPU must prepare a Message Buffer for transmission by executing
the following procedure:
• If the MB is active (transmission pending), write ‘1000’ to the Code field to deactivate the MB.
The deactivated MB can transmit without setting IFLAG and without updating the CODE field (see
Section 24.4.6.2, Message Buffer Deactivation).
• Write the ID word.
• Write the data bytes.
• Write the Length, Control and Code fields of the Control and Status word to activate the MB.
Once the MB is activated in the fourth step, it will participate into the arbitration process and eventually
be transmitted according to its priority. At the end of the successful transmission, the value of the Free
Running Timer is written into the Time Stamp field, the Code field in the Control and Status word is
updated, a status flag is set in the Interrupt Flag Register and an interrupt is generated if allowed by the
corresponding Interrupt Mask Register bit. The new Code field after transmission depends on the code that
was used to activate the MB in step four (see Table 24-5 and Table 24-6 in Section 24.3.2, Message Buffer
Structure). When the Abort feature is enabled (AEN in FLEXCAN_x_MCR is asserted), after the Interrupt
Flag is asserted for a MB configured as transmit buffer, the MB is blocked, therefore the CPU is not able
to update it until the Interrupt Flag be negated by CPU. It means that the CPU must clear the corresponding
IFLAG before starting to prepare this MB for a new transmission or reception.
24.4.3 Arbitration process
The arbitration process is an algorithm executed by the MBM that scans the whole MB memory looking
for the highest priority message to be transmitted. All MBs programmed as transmit buffers will be
scanned to find the lowest ID¹ or the lowest MB number or the highest priority, depending on the LBUF
and LPRIO_EN bits on the Control Register. The arbitration process is triggered in the following events:
• During the CRC field of the CAN frame
• During the error delimiter field of the CAN frame
1. Actually, if LBUF is negated, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID
at the same positions they are transmitted in the CAN frame.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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