PXR40RM Datasheet, PDF (777/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

EDPOL = 1
Time Accumulator
(EMIOS_CCNTR[n])
0xFFFFFF
A1 & B1
Write
A1 Match
Enhanced Modular Input/Output Subsystem (eMIOS200)
A1 & B1
Write
B1 Match
A1 Match
B1 Match
0x000000
Input Signal¹
FLAG Pin/Register
Selected Counter Bus
A1 Value²
B1 Value³
A2 Value⁴
0x000100
0x000100 0x000100
0x001500
Notes: 1. After the input filter
2. EMIOS_CADR[n] = A1
3. EMIOS_CBDR[n] = B1
4. EMIOS_ALTA[n] = A2
0x001500
0x003000
0x003000 0x003000
0x001500 0x004200
A2 ¨ EMIOS_CCNTR[n]
Figure 23-31. WTPA Example
Time
0x004200
0x004200
A2 ¨ EMIOS_CCNTR[n]
23.4.1.1.11 Modulus Counter (MC) Mode
The MC mode can be used to provide a time base for a counter bus or as a general purpose timer.
The MODE[6] bit selects the internal or external clock source when cleared or set, respectively. When the
external clock is selected, the input signal pin is used as the source and the triggering polarity edge is
selected by the EDPOL and EDSEL bits in the EMIOS_CCR[n] register.
The internal counter counts up from the current value until it matches the value in register A1. Register B1
is cleared and is not accessible to the MCU. The MODE[4] bit selects up mode or up/down mode, when
cleared or set, respectively.
When in up count mode, a match between the internal counter and register A1 sets the FLAG and clears
the internal counter. The timing of those events varies according to the MC mode setup as follows:
• Internal counter clearing on match start (MODE = 001_000b)
— When MODE[6] is set, the external clock is selected. In this case, the internal counter clears as
soon as the match signal occurs. The channel FLAG bit is set at the same time the match occurs.
Note that by having the internal counter cleared as soon as the match occurs and incremented
at the next input event, a shorter zero count is generated. See Figure 23-61 and Figure 23-63.
— When MODE[6] is cleared, the internal clock source is selected. In this case, the counter clears
as soon as the match signal occurs. The channel FLAG bit is set at the same time the match
occurs. At the next prescaler tick after the match, the internal counter remains at 0 and only
resumes counting on the following tick. See Figure 23-61 and Figure 23-64.
• Internal counter clearing on match end (MODE = 001_001b)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-37