PXR40RM Datasheet, PDF (1115/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 28
Decimation Filter
28.1 Overview
This document describes the Decimation Filter block functionality for the PXR40 Rev 2 device, and is not
valid for any other revisions of this device.
There are 12 independent Decimation Filter blocks (A through L) on the device. Each Decimation Filter
block contains a multiply-accumulate (MAC) unit capable of implementing a 16-bit, 4th order IIR or 8th
order FIR filter. The Decimation Filter blocks can be cascaded to create larger filters. Filter output data can
be decimated at a programmable rate in the range 1 to 16.
Each Decimation Filter has a 32-bit integrator unit, which allows the block to accumulate and sum a series
of filter outputs. The integrator input can be selected from before or after the decimator. The integrator can
be enabled and disabled, cleared, and read by software or by hardware triggers from certain channels of
the eTPU modules on the device. The integrator control triggers are selected in the SIU_DECFIL1 and
SIU_DECFIL2 and SIU_DECFIL3 registers.
The data and control registers for each Decimation Filter block are independently accessed by the CPU.
All Decimation Filters support DMA writes to the input data register, and DMA reads of the output data
register. The eQADC_A and eQADC_B blocks have an internal hardware link to Decimation Filters A
through L. This allows CPU independent transfer of eQADC_A and eQADC_B analog to digital
conversion result data to the Decimation Filter input data registers, and filter output data back to the
eQADC_A and eQADC_B conversion result FIFOs.
Each Decimation Filter block supports 4 combinations of input data source and output result destination:
1. Input from eQADC/Output to eQADC: In this mode, the Decimation Filter receives analog to
digital conversion data samples from the eQADC block. The output result from the Decimation
Filter is automatically returned to the RFIFO in eQADC that was specified in the conversion
command for the ADC input.
2. Input from system RAM/Output to system RAM: In this mode, the input data to the Decimation
filter is supplied from system RAM by the CPU or DMA. The filter data and associated commands
are written to a memory mapped input register, and the output results are written to a memory
mapped register, where they can be read by either CPU or DMA.
3. Input from eQADC/Output to system RAM: In this mode, the Decimation Filters can be
configured for input data from eQADC and output result to the system RAM (CPU or DMA).
4. Input from system RAM/Output to eQADC: In this mode, the Decimation Filter input data from
system RAM (CPU or DMA), and the output result is sent to an eQADC result FIFO.
Each Decimation Filter block can be programmed to generate interrupt requests when input data is
received from the eQADC, when the filter result is written to the output buffer, if a filter overflow occurs,
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-1