PXR40RM Datasheet, PDF (871/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 25-5. DSPI_MCR Field Descriptions (continued)
Field
Description
17
MDIS
Module Disable. The MDIS bit allows the clock to be stopped to the non-memory mapped logic in the
DSPI effectively putting the DSPI in a software controlled power-saving state. See Section 25.4.11,
Power Saving Features, for more information.
0 Enable DSPI clocks.
1 Allow external logic to disable DSPI clocks.
18
DIS_TXF
Disable Transmit FIFO. The DIS_TXF bit provides a mechanism to disable the TX FIFO. When the TX
FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI. See
Section 25.4.3.3, FIFO Disable Operation, for details.
0 TX FIFO is enabled
1 TX FIFO is disabled
19
DIS_RXF
Disable Receive FIFO. The DIS_RXF bit provides a mechanism to disable the RX FIFO. When the
RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI. See
Section 25.4.3.3, FIFO Disable Operation, for details.
0 RX FIFO is enabled
1 RX FIFO is disabled
20
CLR_TXF
Clear TX FIFO. CLR_TXF is used to flush the TX FIFO. Writing a ‘1’ to CLR_TXF clears the TX FIFO
Counter. The CLR_TXF bit is always read as zero.
0 Do not clear the TX FIFO Counter
1 Clear the TX FIFO Counter
21
CLR_RXF
Clear RX FIFO. CLR_RXF is used to flush the RX FIFO. Writing a ‘1’ to CLR_RXF clears the RX
Counter. The CLR_RXF bit is always read as zero.
0 Do not clear the RX FIFO Counter
1 Clear the RX FIFO Counter
22–23 SMPL_PT — Sample Point. SMPL_PT allows the host software to select when the DSPI Master
SMPL_PT samples SIN in Modified Transfer Format. Figure 25-31 shows where the Master can sample the SIN
pin. The table below lists the various delayed sample points.
SMPL_PT
Number of system clock cycles between odd-numbered edge of
SCK and sampling of SIN.
00
0
01
1
10
2
11
Reserved
24–30
31
HALT
Reserved, should be cleared.
Halt. The HALT bit provides a mechanism by software to start and stop DSPI transfers. See
Section 25.4.2, Start and Stop of DSPI Transfers, for details on the operation of this bit.
0 Start transfers
1 Stop transfers
25.3.2.2 DSPI Transfer Count Register (DSPI_TCR)
The DSPI_TCR contains a counter that indicates the number of SPI transfers made. The transfer counter
is intended to assist in queue management. The user must not write to the DSPI_TCR while the DSPI is in
the Running state.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-11