PXR40RM Datasheet, PDF (148/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Power Management Controller (PMC)
A weak pull down of about 100 k is added to ensure the selection of the LDO regulator even when the
signal REGSEL is not connected at board level.
5.5.2 PMC Bandgap
An accurate band gap voltage is used in the PMC as reference for regulators and LVDs. Target band gap
voltage VBG is 0.62V with variation defined in PXR40 Microcontroller Data Sheet.
During factory test, the bandgap is calibrated in curvature and absolute value, in order to achieve a good
accuracy over temperature range and supply voltage variation.
5.5.3 VDDREG LVD
A user programmable low voltage detector (LVD) monitors the PMC main supply voltage VDDREG.
When LDO regulator is selected, with respective selection pin REGSEL, the LVD threshold is for a
nominal 3.3V supply (both LDO3V and LDO5V modes), else when the SMPS regulator is selected the
LVD threshold is nominal 5.0V (SMPS5V mode).
Rising LVD threshold voltage is documented under LvdReg symbol in the PXR40 Microcontroller Data
Sheet.
The assertion and negation voltages are adjustable via software by writing to the LVDREGTRIM field of
the PMC_TRIMR register, which selects one of the 16 voltages available through the appropriate tapped
output. The reset and default value of the 4-bit register is “1111”, corresponding to the nominal LvdReg
voltage.
LVD scaled voltage can be measured via ADC by selecting the respective channel reported in Table 5-8.
During this measurement, the output of the LVD is temporarily forced to low level so that false events,
which may be caused by ADC reading, are discarded.
5.5.4 3.3V Internal Voltage Regulator
A 3.3V internal voltage regulator is available and it can supply a total DC current of IDD33 with a
maximum load frequency of 10 kHz. The board should be designed to dump all current overshoots and
undershoots, by having the VDDSYN pin connected to decoupling capacitors. The recommended external
capacitor range may vary between 220 nF and 2.2 µF with ESR < 100 m.
This regulator is always enabled when supply voltage VDDREG is in the VDDR 5V nominal range. When
the supply voltage is in the VDDR 3V nominal range the regulator is automatically turned off, so that an
external supply can be applied. In this case VDDREG and VDDSYN must be connected to the same
supply voltage with a maximum voltage difference of 200mV.
The regulator can be disabled, so that an external 3.3 V supply can be used (see Section 5.1.1, Features).
In this case it is recommended that the supplied 3.3V is nominal 3.5V +/- 3% during start up when both
regulators may be enabled. For the correct operation of the device the externally supplied VDD33 voltage
must be higher than the maximum correspondent LVD rising voltage LVD33.
5-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor