PXR40RM Datasheet, PDF (1188/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
1 = Negate Global Exception, clear status bits ILF1, ILF2, MGE1, MGE2, and SCMMISF.
0 = Keep Global Exception request and status bits ILF1, ILF2, MGE1, MGE2, and SCMMISF as is.
GEC works the same way with either one or both Engines in Module Disable Mode.
WDTO1,2 — Watchdog Timeout
Flags WDTO1 and WDTO2 indicate that a Watchdog Timeout occurred in eTPU engine A or C and
eTPU engine B respectively, generating a Global Exception. These bits are cleared by writing 1 to
GEC.
1 = Global Exception requested by Watchdog timeout
0 = No Global Exception pending because of Watchdog timeout.
MGE1,2— Microcode Global Exception - Engine A, B
These bits indicate that a Global Exception was asserted by microcode executed on the respective
Engine. The determination of the reason why the Global Exception was asserted is application
dependent: it can be coded in an SDM status parameter, for instance. This bit is cleared by writing 1
to GEC.
1 = Global Exception requested by microcode is pending
0 = No microcode-requested Global Exception pending.
ILF1,2— Illegal Instruction Flag - eTPU A, B
The ILF1/2 bit is set by the microengine to indicate that an illegal instruction was decoded in Engine
1/2. This bit is cleared by host writing 1 to GEC. See the eTPU Reference Manual for more details.
1 = Illegal Instruction detected by eTPU A, B.
0 = Illegal Instruction not detected.
SCMSIZE[0:4] - SCM Size
This read-only field holds the number of 2 Kbyte SCM Blocks minus 1. This value is 11 for eTPU A/B
and 5, meaning SCM sizes of 24 Kbyte, respectively.
SCMMISC, SCMMISCC — SCM MISC Complete, SCM MISC Complete Clear
Flag SCMMISC indicates that MISC has completed the evaluation of the SCM signature since reset
or the since the last time it was cleared. SCMMISC is cleared by writing 1 to SCMMISCC (at same bit
position), and is not cleared when MISC is disabled (SCMMISEN=0). SCMMISC asserts at the end
of the SCM memory scan, either if the signature matches or not.
1 = MISC completed at least one SCM signature calculation and compare since the last time
SCMMISC was cleared.
0 = MISC has not yet completed an SCM signature calculation and compare since the last time
SCMMISC was cleared.
SCMMISF— SCM MISC Flag
The SCMMISF bit is set by the SCM MISC (Multiple Input Signature Calculator) logic to indicate that
the calculated signature does not match the expected value, at the end of a MISC iteration. See
Section 29.3.6.1, SCM Test - Multiple Input Signature Calculator, for more details.
1 = MISC has read entire SCM array and the expected signature in ETPUMISCCMPR does not
match the value calculated.
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor