PXR40RM Datasheet, PDF (1202/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
WDCNT[15:0] — Watchdog Count
This field indicates the maximum number of microcycles allowed for a thread (in thread length mode)
or a sequence of threads (in busy length mode) before the current running thread is forced to end. For
more information on Watchdog operation, see Section 29.3.1, Watchdog.
NOTE
The TST microcycles are also counted by the watchdog.
29.2.7.2 ETPUIDLER - eTPU Idle Register
This register counts the microcycles in which the microengine is idle (see Section 29.3.7.1, Idle Counter).
eTPU A: Base + 0x068 / eTPU B: Base + 0x078
0
1
2
3
4
5
R
W
RESET: 0
0
0
0
0
0
6
7
8
9
IDLE_CNT[31:16]
0
0
0
0
10
11
12
13
14
15
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
IDLE_CNT[15:0]
W
ICLR
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-13. ETPUIDLER Register
IDLE_CNT[31:0] — Idle Count
This is a free-running count of the number of idle microcycles in the microengine. For more
information on idle counter operation, see Section 29.3.7.1, Idle Counter.
ICLR — Idle Clear
This write-only bit is used to clear the idle count IDLE_CNT:
1 = clear the idle count IDLE_CNT
0 = do not clear idle count IDLE_CNT
29.2.8 Channel Registers Layout
The channel registers area is shown in Figure 29-14 and detailed in next sections, for eTPU systems of 32
channels per Engine. Reserved areas are placed to allow doubling the number of channels to 64 for each
eTPU Engine.
29-34
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor