PXR40RM Datasheet, PDF (451/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Field
Table 15-4. PBRIDGE_x_MPCR Field Descriptions
Description
Peripheral Bridge (PBRIDGE)
n = XBAR Port
Number
0
CPU core
1
Nexus
4
eDMA A
5
eDMA B
6
FlexRay
Master
0
4
16
20
24
MBWn
1
5
17
21
25
MTRn
2
6
18
22
26
MTWn
3
7
19
23
27
MPLn
8–15
28–31
Master buffer writes. Determines whether the PBRIDGE is enabled to buffer writes from the master. Buffered
writes are disabled by default.
0 Buffered write accesses from the master are disabled
1 Buffered write accesses from the master are enabled
Master trusted for reads. Determines whether the master is trusted for read accesses. Trusted by default.
0 Read accesses from the module are not trusted
1 Read accesses from the module are trusted
Master trusted for writes. Determines whether the master is trusted for write accesses. Trusted by default.
0 Write accesses from the master are not trusted
1 Write accesses from the master are trusted
Master privilege level. Determines how the privilege level of the master is determined. Accesses not forced to
user mode by default.
0 Accesses from the master are forced to user mode
1 Accesses from the master are not forced to user mode
Reserved
15.3.1.2 Peripheral Access Control Registers (PBRIDGE_x_PACR) and
Off-Platform Peripheral Access Control Registers (PBRIDGE_x_OPACR)
Each of the PBRIDGE on-platform peripherals has a 4-bit access field in a peripheral access control
register (PACR) that defines the access levels supported by the given module. A single PACR contains up
to eight of these module-access fields, and the PACR register structure is shown in Table 15-2 and
Table 15-3. The PACR registers with their access fields are shown in Figure 15-3. There are three PACR
registers, one for bridge A and two for bridge B.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
15-7