PXR40RM Datasheet, PDF (257/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Table 7-50. SIU_PGPDI0 - SIU_PGPDI15 - SIU_PGPDO15 Field Descriptions
Field
0–31
PGPDIx
Description
Pin Data In. Stores the value of the pad-interface signals (data in) corresponding to the external GPIO pin
associated with the register.
0 The value of the pad-interface signals (data in) for the corresponding GPIO pin is logic low.
1 The value of the pad-interface signals (data in) for the corresponding GPIO pin is logic high.
7.3.1.32 Masked Parallel GPIO Pin Data Output Register (SIU_MPGPDO0 -
SIU_MPGPDO31)
The MPGPDOx registers are written to by software to drive data out on the external GPIO pin (they are
write-only registers and reading them will return 0; reading must be done by accessing the corresponding
SIU_GPDO register). These registers access the same GPIO pins accessed by SIU_GPDO0–
SIU_GPDO511 bit registers. The most significant 16 bits in the SIU_MPGPDO registers should map
directly to these registers. For example, SIU_MPGPDO0 bit 31 is SIU_GPDO15 bit 7, SIU_MPGPDO0
bit 30 is SIU_GPDO17 bit 7,...., SIU_MPGPD15 bit 16 is SIU_GPDO240 bit 7. The least significant
sixteen bits are the corresponding values to be written at GPIO pins defined by MASK field. The masked
parallel GPIO read/write should be decode the logical addresses to the same physical address of the normal
GPIO.
SIU_BASE + 0xC80 - SIU_BASE + 0xCFC (32)
R
W
RESET:
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK MASK
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA DATA
W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
RESET: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-30. Masked Parallel GPIO Pin Data Output Register (SIU_MPGPDO0 - SIU_MPGPDO31)
Table 7-51. SIU_MPGPDO0 - SIU_MPGPDO31 Field Descriptions
Field
0–15
MASKx
16–31
DATAx
Description
Pin Data Out. Controls the write access to the corresponding GPDO.
0 Previous value defined by GPDO is maintain.
1 Corresponding GPDO is written with value defined by DATA field.
Pin Data Out. Stores the data to be driven out on the external GPIO pin controlled by this register.
0 Logic low value is driven on the pad interface data out signal for the corresponding GPIO pin when the
pin is configured as an output.
1 Logic high value is driven on the pad interface data out signal for the corresponding GPIO pin when the
pin is configured as an output.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-75