PXR40RM Datasheet, PDF (421/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
Table below lists register settings when an alignment interrupt is taken.
Table 13-22. Alignment Interrupt—Register Settings
Register
Setting Description
SRR0
SRR1
MSR
ESR
MCSR
DEAR
Vector
Set to the effective address of the excepting load/store instruction.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
FE1 0
IS 0
DS 0
PMM 0
RI —
[ST], [SPE], [VLEMI]. All other bits cleared.
Unchanged
Set to the effective address of a byte of the load or store whose access caused the violation.
IVPR_0:15 || IVOR5_16:27 || 4b0000
13.9.7 Program Interrupt (IVOR6)
A program interrupt occurs when no higher priority exception exists and one or more of the following
exception conditions occur:
• Illegal Instruction exception
• Privileged Instruction exception
• Trap exception
• Unimplemented Operation exception
The PXR40 will invoke an Illegal Instruction program exception on attempted execution of the following
instructions:
• Unimplemented instructions
• Instruction from the illegal instruction class
• mtspr and mfspr instructions with an undefined SPR specified
• mtdcr and mfdcr instructions with an undefined DCR specified
The PXR40 will invoke a Privileged Instruction program exception on attempted execution of the
following instructions when MSR_PR=1 (user mode):
• A privileged instruction
• mtspr and mfspr instructions which specify a SPRN value with SPRN₅=1 (even if the SPR is
undefined).
The PXR40 will invoke a Trap exception on execution of the tw and twi instructions if the trap conditions
are met and the exception is not also enabled as a Debug interrupt.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-33