PXR40RM Datasheet, PDF (503/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Software Watchdog Timer (SWT)
Table 18-6. SWT_SR Field Descriptions
Field
Description
0–15 Reserved
16–31 Watchdog Service Code.This field is used to service the watchdog and to clear the soft lock bit
WSC (SWT_MCR[SLK]). If the SWT_MCR[KEY] bit is set, two pseudorandom key values are written to service
the watchdog, see section Section 18.4, Functional Description, for details. Otherwise, the sequence
0xA602 followed by 0xB480 is written to the WSC field. To clear the soft lock bit (SWT_MCR[SLK]), the value
0xC520 followed by 0xD928 is written to the WSC field.
18.3.2.6 SWT Counter Output Register (SWT_CO)
The SWT Counter Output (SWT_CO) register is a read only register that shows the value of the internal
down counter when the SWT is disabled.
Offset 0x014
Access: Read Only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
CNT
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-6. SWT Counter Output Register (SWT_CO)
Table 18-7. SWT_CO Register Field Descriptions
Field
Description
0–31
CNT
Watchdog Count. When the watchdog is disabled (SWT_MCR[WEN]=0) this field shows the value of the
internal down counter. When the watchdog is enabled the value of this field is 0x0000_0000. Values in this
field can lag behind the internal counter value for up to six system plus eight counter clock cycles.
Therefore, the value read from this field immediately after disabling the watchdog may be higher than the
actual value of the internal counter.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
18-7