PXR40RM Datasheet, PDF (883/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Field
0
CONT
1–3
CTAS
Table 25-16. DSPI_PUSHR Field Descriptions
Descriptions
Continuous Peripheral Chip Select Enable. The CONT bit selects a Continuous Selection Format. The
bit is used in SPI Master Mode. The bit enables the selected PCS signals to remain asserted between
transfers. See Section 25.4.7.5, Continuous Selection Format, for more information.
0 Return Peripheral Chip Select signals to their inactive state between transfers
1 Keep Peripheral Chip Select signals asserted between transfers
Clock and Transfer Attributes Select. The CTAS field selects which of the DSPI_CTAR register is used
to set the transfer attributes for the associated SPI frame. The field is only used in SPI Master Mode.
In SPI Slave Mode DSPI_CTAR0 is used. The table below shows how the CTAS values map to the
DSPI_CTAR registers. The number of DSPI_CTAR registers is implementation specific.
CTAS
000
001
010
011
Use Clock and Transfer
Attributes from
DSPI_CTAR0
DSPI_CTAR1
DSPI_CTAR2
DSPI_CTAR3
CTAS
100
101
110
111
Use Clock and Transfer
Attributes from
DSPI_CTAR4
DSPI_CTAR5
DSPI_CTAR6
DSPI_CTAR7
4
EOQ
5
CTCNT
6–9
10–15
PCSx
16–31
TXDATA
End Of Queue. The EOQ bit provides a means for host software to signal to the DSPI that the current
SPI transfer is the last in a queue. At the end of the transfer the EOQF bit in the DSPI_SR is set.
0 The SPI data is not the last data to transfer
1 The SPI data is the last data to transfer
Clear SPI_TCNT. The CTCNT provides a means for host software to clear the SPI transfer counter.
The CTCNT bit clears the SPI_TCNT field in the DSPI_TCR register. The SPI_TCNT field is cleared
before transmission of the current SPI frame begins.
0 Do not clear SPI_TCNT field in the DSPI_TCR
1 Clear SPI_TCNT field in the DSPI_TCR
Reserved, should be cleared
Peripheral Chip Select 0–5. The PCS bits select which PCS signals will be asserted for the transfer.
0 Negate the PCS[x] signal
1 Assert the PCS[x] signal
Transmit Data. The TXDATA field holds SPI data to be transferred according to the associated SPI
command.
25.3.2.7 DSPI POP RX FIFO Register (DSPI_POPR)
The DSPI_POPR provides a means to read the RX FIFO. See Section 25.4.3.5, Receive First In First Out
(RX FIFO) Buffering Mechanism, for a description of the RX FIFO operations. Eight or sixteen bit read
accesses to the DSPI_POPR will read from the RX FIFO and update the counter and pointer.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-23