PXR40RM Datasheet, PDF (249/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
7.3.1.24 External Clock Control Register (SIU_ECCR)
The SIU_ECCR controls the timing relationship between the system clock and the external clocks
ENGCLK and CLKOUT. All bits and fields in the SIU_ECCR are read/write and are reset by the internal
reset condition.
Address: SIU_BASE + 0x0984
Access: R/W
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
R0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
0
0
0
0
ENGDIV
ECSS
EBTS
EBDF
W
Reset 0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
Figure 7-22. External Clock Control Register (SIU_ECCR)
The following table describes the external clock control fields:
Table 7-44. SIU_ECCR Bit Field Descriptions
Field
0–15
16–23
ENGDIV
Description
Reserved
Engineering clock division factor. Specifies the frequency ratio between f_periph (also
referred to as f_platf on this device) and ENGCLK. The ENGCLK frequency is divided from
f_platf according to the following equation:
Engineering clock frequency = ---------f--^p---^e--^r--ⁱ--^p--^h----------
ENGDIV  2
The maximum ENGCLK frequency is 66 MHz (132 MHz  2)
24
ECSS
25–27
28
EBTS
Note: Setting ENGDIV to 0 makes the ENGCLK frequency equal to the f_periph.
Engineering clock (ENGCLK) source select.
0 The system clock is the source of the ENGCLK.
1 The external clock (the EXTAL frequency of the oscillator) is the source of the ENGCLK.
Reserved
External bus tap select. Changes the phase relationship between the system clock and
CLKOUT. Changing the phase relationship so that CLKOUT is advanced in relation to the
system clock increases the output hold time of the external bus signals to a non-zero
value. It also increases the output delay times, increases the input hold times to non-zero
values, and decreases the input setup times. Refer to the Electrical Specifications for how
the EBTS bit affects the external bus timing.
0 External bus signals have zero output hold times.
1 External bus signals have non-zero output hold times.
Note: Do not change EBTS while an external bus transaction is in process.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-67