PXR40RM Datasheet, PDF (1403/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
defines the set of data registers that can operate and interact with the on-chip system logic while the
instruction is current. Only one test data register path is enabled to shift data between TDI and TDO for
each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the EXTEST,
SAMPLE or SAMPLE/PRELOAD instructions are active. The single-bit bypass register shift stage is
enabled for serial access between TDI and TDO when the HIGHZ, CLAMP or reserved instructions are
active. The functionality of each test mode is explained in more detail in Section 32.4.4, JTAGC
Instructions.
32.1.4.3 Bypass Mode
When no test operation is required, the BYPASS instruction can be loaded to place the JTAGC into bypass
mode. While in bypass mode, the single-bit bypass shift register is used to provide a minimum-length
serial path to shift data between TDI and TDO.
32.1.4.4 TAP Sharing Mode
The selectable auxiliary TAP controllers that share the TAP with the JTAGC are:
• Nexus port controller (NPC)
• e200 OnCE
• eTPU Nexus
• eDMA A Nexus
• eDMA B Nexus
• FlexRay
The instructions required to grant ownership of the TAP to the auxiliary TAP controllers are:
• ACCESS_AUX_TAP_NPC
• ACCESS_AUX_TAP_ONCE
• ACCESS_AUX_TAP_eTPU
• ACCESS_AUX_TAP_DMA_A
• ACCESS_AUX_TAP_DMA_B
• ACCESS_AUX_TAP_NXFR
Instruction opcodes for each instruction are shown in Table 32-3.
When the access instruction for an auxiliary TAP is loaded, control of the JTAG pins is transferred to the
selected TAP controller. Any data input via TDI and TMS is passed to the selected TAP controller, and any
TDO output from the selected TAP controller is sent back to the JTAGC to be output on the pins. The
JTAGC regains control of the JTAG port during the UPDATE-DR state if the PAUSE-DR state was
entered. Auxiliary TAP controllers are held in RUN-TEST/IDLE while they are inactive.
For more information on the TAP controllers refer to Chapter 31, Nexus Development Interface (NDI).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
32-3