PXR40RM Datasheet, PDF (554/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
21.3.2.13 eDMA Interrupt Request Registers (EDMA_A_IRQRH, EDMA_x_IRQRL)
The EDMA_A_IRQRH and EDMA_x_IRQRL provide a bit map for the 32 channels signaling the
presence of an interrupt request for each channel. EDMA_A_IRQRH maps to channels 63–32 and
EDMA_x_IRQRL maps to channels 31–0.
The DMA engine signals the occurrence of a programmed interrupt on the completion of a data transfer
as defined in the transfer control descriptor by setting the appropriate bit in this register. The outputs of
this register are directly routed to the interrupt controller (INTC). During the execution of the interrupt
service routine associated with any given channel, software must clear the appropriate bit, negating the
interrupt request. Typically, a write to the EDMA_x_CIRQR in the interrupt service routine is used for this
purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the EDMA_x_CIRQR. On writes to the EDMA_A_IRQRH or EDMA_x_IRQRL,
a 1 in any bit position clears the corresponding channel’s interrupt request. A 0 in any bit position has no
effect on the corresponding channel’s current interrupt status. The EDMA_x_CIRQR is provided so the
interrupt request for a single channel can be cleared.
Address: EDMA_A_BASE + 0x0020
Access: User R/W
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT}
W ^{63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT}
W ^{47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-17. eDMA Interrupt Request High Register (EDMA_A_IRQRH)
Address: EDMA_x_BASE + 0x0024
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT}
W ^{31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
19
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT INT}
W ^{15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-18. eDMA Interrupt Request Register (EDMA_x_IRQRL)
21-30
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor