PXR40RM Datasheet, PDF (1055/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Interrupt Status Registers (EQADC_FISR), is not decremented by one, and Transfer Next Data Pointer 0
is incremented by one (or wrapped around) to point to the next entry in the CFIFO0.
Write to slave-bus
interface by CPU or
DMA
CFIFO
Push Register
Repeat
Pointer
Push Next
Data Pointer *
DMA Done
Interrupt/DMA Request
32-bit Entry n, Rep
--------------------
--------------------
32-bit Entry 2
32-bit Entry 1
Control
Signals
CFIFO
Transfer Counter
Control Logic
Transfer Next
Data Pointer *
Data to
external
device or
to on-chip
ADCs
* All CFIFO entries are memory mapped and the
entries addressed by these pointers can have their
absolute addresses calculated using TNXTPTR and
CFCTR.
Figure 27-51. CFIFO0 in Streaming Mode Diagram
The detailed behavior of the Push Next Data Pointer and Transfer Next Data Pointer is described in the
example shown in Figure 27-52 where a CFIFO with 16 entries is shown for clarity of explanation, the
actual hardware implementation has only four/eight entries. In this example, CFIFO0 with 16 entries is
shown in sequence after pushing and transferring entries.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-73