PXR40RM Datasheet, PDF (545/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
EDMA_x_TCD.D_REQ bit is set, then the corresponding EDMA_x_ERQR bit is cleared after the major
loop is complete, disabling the eDMA hardware request. Otherwise if the D_REQ bit is cleared, the state
of the EDMA_x_ERQR bit is unaffected.
21.3.2.4 eDMA Enable Error Interrupt Registers (EDMA_A_EEIRH,
EDMA_x_EEIRL)
NOTE
Any reference to EDMA_A_[register_name] should be ignored when using
eDMA_B. That register does not exist in eDMA_B. Registers that exist in
both eDMA_A and eDMA_B are indicated with a register name of format
EDMA_x_[register_name].
The EDMA_A_EEIRH and EDMA_x_EEIRL provide a bit map for the 32 (or 64 for eDMA_A) channels
to enable the error interrupt signal for each channel. EDMA_A_EEIRH supports channels 63–32, while
EDMA_x_EEIRL covers channels 31–0.
The state of any given channel’s error interrupt enable is directly affected by writes to these registers; it is
also affected by writes to the EDMA_x_SEEIR and EDMA_x_CEEIR. The EDMA_x_SEEIR and
EDMA_x_CEEIR are provided so that the error interrupt enable for a single channel can be modified
without the performing a read-modify-write sequence to the EDMA_A_EEIRH and EDMA_x_EEIRL.
Both the eDMA error indicator and this error interrupt enable flag must be asserted before an error
interrupt request for a given channel is asserted.
Address: EDMA_A_BASE + 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R _{EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI}
W ^{63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R _{EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI EEI}
W ^{47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32}
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 21-7. eDMA Enable Error Interrupt High Register (EDMA_A_EEIRH)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-21