PXR40RM Datasheet, PDF (938/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Field
RWU
SBK
Table 26-6. eSCI_CR1 Field Descriptions (continued)
Description
Receiver Wake-Up Mode. This bit controls and indicates the receiver wake-up mode, which is described in
Section 26.4.5.5, Multiprocessor Communication.
0 Normal receiver operation.
1 Receiver is in wake-up mode.
Note: This bit should be set in SCI mode only.
Send Break Character. This bit controls the transmission of break characters, which is described in
Section 26.4.5.2.7, Break Character Transmission.
0 No break characters will be transmitted.
1 Break characters will be transmitted.
Note: This bit should be set in SCI mode only.
Table 26-7. Receive Source Mode Selection
LOOPS
0
0
1
1
RSCR
0
1
0
1
Receiver Input Mode
Dual Wire Mode
Reserved
Loop Mode
Single Wire Mode
26.3.2.3 Control Register 2 (eSCI_CR2)
eSCI_BASE + 0x0004
Write: Anytime
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
W ^{MDIS FBR BSTP}
BRCL
BESM BESTP
PMSK ORIE NFIE FEIE PFIE
Reset 0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-4. Control Register 2 (eSCI_CR2)
This register provides bits to configure the functionality of the module, and interrupt enable bits for the
interrupt flags provided in Interrupt Flag and Status Register 1 (eSCI_IFSR1) and control bits for the
transmitter and receiver.
Table 26-8. eSCI_CR2 Field Descriptions
Field
MDIS
FBR
Description
Module Disabled Mode. This bit controls the Module Mode of Operation, which is described in Section 26.1.6,
Modes of Operation
0 Module is not in Disabled Mode.
1 Module is in Disabled Mode.
Fast Bit Error Detection. This bit controls the Bit Error Detection mode.
0 Standard Bit error detection performed as described in Section 26.4.6.5.3, Standard Bit Error Detection.
1 Fast Bit error detection performed as described in Section 26.4.6.5.4, Fast Bit Error Detection.
Note: This bit is used in LIN mode only.
26-10
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor