PXR40RM Datasheet, PDF (499/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Software Watchdog Timer (SWT)
Offset 0x0000
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R MAP MAP 0
0 MAP MAP MAP MAP 0
0
0
0
0
0
0
0
0
1
W
4
5
6
7
Reset 1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R0
0
0
0
0
0 KEY RIA WND ITR HLK SLK CSL STP FRZ WEN
W
Reset 0
0
0
0
0
0
*
1
0
0
0
0
1
0
1
1
Figure 18-1. SWT Control Register (SWT_MCR)
Table 18-2. SWT_MCR Field Descriptions
Field
0–1
4–7
MAPn
Master Access Protection for Master n
0 = Access for the master is not enabled
1 = Access for the master is enabled
Description
Master IDs are listed in Table 14-1.
2–3
8–21
22
KEY
23
RIA
24
WND
25
ITR
26
HLK
27
SLK
Once set, MAPn bit is cleared only by other masters that are not disabled, or only after the reset.
Reserved
Keyed Service Mode.
0 = Fixed Service Sequence, the fixed sequence 0xA602, 0xB480 is used to service the watchdog
1 = Keyed Service Mode, two pseudorandom key values are used to service the watchdog
Reset on Invalid Access.
0 = Invalid access to the SWT generates a bus error
1 = Invalid access to the SWT causes a system reset if WEN=1 (watchdog enabled)
Window Mode.
0 = Regular mode, service sequence can be done at any time
1 = Windowed mode, the service sequence is only valid when the down counter is less than the value in
the SWT_WN register.
Interrupt Then Reset.
0 = Generate a reset on a time-out
1 = Generate an interrupt on an initial time-out, reset on a second consecutive time-out
Hard Lock. This bit is only cleared at reset.
0 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read/write registers if SLK=0
1 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read only registers
Soft Lock. This bit is cleared by writing the unlock sequence to the service register.
0 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read/write registers if HLK=0
1 = SWT_MCR, SWT_TO, SWT_WN and SWT_SK are read only registers
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
18-3