PXR40RM Datasheet, PDF (1028/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
27.6.3.2 ADC Time Stamp Control Register (ADC_TSCR)
The ADC Time Stamp Control Register (ADC_TSCR) contains a platform clock divide factor used in the
making of the time base counter clock. It determines at what frequency the time base counter will run.
ADC_TSCR can be accessed by configuration commands sent to CBuffer0 or to CBuffer1. A data write
to ADC_TSCR through a configuration command sent to CBuffer0 will write the same memory location
as when writing to it through a configuration command sent to CBuffer1.
NOTE
Simultaneous write accesses from CBuffer0 and CBuffer1 to ADC_TSCR
are not allowed.
ADC0/1 Register Address: 0x02
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R0
0
0
0
0
0
0
0
0
0
0
0
W
TBC_CLK_PS
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 27-34. ADC Time Stamp Control Register (ADC_TSCR)
Table 27-23. ADC_TSCR Field Descriptions
Field
0–11
12–15
TBC_CLK_PS
Description
Reserved
Time Base Counter Clock Prescaler. The TBC_CLK_PS field contains the platform clock divide factor for
the time base counter. It controls the accuracy of the time stamp. The prescaler is disabled when
TBC_CLK_PS is set to 0b0000.
Table 27-24. Clock Divide Factor for Time Stamp
TBC_CLK_PS[0:3]
0b0000
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
0b1001
0b1010
0b1011
0b1100
Platform Clock Divide
Factor
Disabled
1
2
4
6
8
10
12
16
32
64
128
256
Clock to Time Stamp
Counter for a 120 MHz
Platform Clock (MHz)
Disabled
120
60
30
20
15
12
10
7.5
3.75
1.88
0.94
0.47
27-46
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor