PXR40RM Datasheet, PDF (815/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

24.2 External Signal Description
FlexCAN Module
24.2.1 Overview
The FlexCAN module has two I/O signals connected to the external MCU pins. These signals are
summarized in Table 24-1 and described in more detail in the next subsections.
Table 24-1. FlexCAN Signals
Signal Name¹
Direction
Description
CAN Rx
CAN Tx
Input
Output
CAN Receive Pin
CAN Transmit Pin
NOTES:
1 _{The actual MCU pins may have different names. Please consult the Device User}
Guide for the actual signal names.
24.2.2 Signal Descriptions
24.2.2.1 CAN Rx
This pin is the receive pin from the CAN bus transceiver. Dominant state is represented by logic level ‘0’.
Recessive state is represented by logic level ‘1’.
24.2.2.2 CAN Tx
This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by logic level ‘0’.
Recessive state is represented by logic level ‘1’.
24.3 Memory Map/Register Definition
This section describes the registers and data structures in the FlexCAN module. The base address of the
module depends on the particular memory map of the MCU. The addresses presented here are relative to
the base address.
The address space occupied by FlexCAN has 96 bytes for registers starting at the module base address,
followed by MB storage space in embedded RAM starting at address 0x0060, and an extra ID Mask
storage space in a separate embedded RAM starting at address 0x0880.
24.3.1 FlexCAN Memory Mapping
The complete memory map for a FlexCAN module with 64 MBs capability is shown in Table 24-2. Each
individual register is identified by its complete name and the corresponding mnemonic. The access type is
always Supervisor (S).
The FLEXCAN_x_IFLAG2 and FLEXCAN_x_IMASK2 registers are considered reserved space when
FlexCAN is configured with 16 or 32 MBs. The Rx Global Mask (FLEXCAN_x_RXGMASK), Rx Buffer
14 Mask (FLEXCAN_x_RX14MASK) and the Rx Buffer 15 Mask (FLEXCAN_x_RX15MASK)
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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