PXR40RM Datasheet, PDF (904/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
of how a DSPI can be used with a deserializing peripheral that supports SPI control for control and
diagnostic frames.
DSPI Master
Shift Register
TX Priority
Control
SPI
TX FIFO
DSI
SIN
SOUT
SCK
PCSx
PCSy
SOUT
SIN
SCK
External Slave Deserializer
Shift Register
SSx _Frame
SSy
Select
Logic
SPI
DSI
Frame Frame
Figure 25-24. Example of System using DSPI in CSI Configuration
In CSI Configuration the DSPI transfers DSI data based on DSI Transfer Initiation Control. When there
are SPI commands in the TX FIFO, the SPI data has priority over the DSI frames. When the TX FIFO is
empty, DSI transfer resumes.
Two peripheral chip select signals indicate whether DSI data or SPI data is transmitted. The user must
configure the DSPI so that the two CTAR registers associated with DSI data and SPI data assert different
peripheral chip select signals denoted in the figure as PCSx and PCSy. The CSI Configuration is only
supported in Master Mode.
Data returned from the external slave while a DSI frame is transferred is placed on the Parallel Output
signals. Data returned from the external slave while a SPI frame is transferred is moved to the RX FIFO.
The TX FIFO and RX FIFO are fully functional in CSI mode.
25.4.5.1 CSI Serialization
Serialization in the CSI configuration is similar to serialization in DSI Configuration. The transfer
attributes for SPI frames are determined by the DSPI_CTAR register selected by the CTAS field in the SPI
command halfword. The transfer attributes for the DSI frames are determined by the DSPI_CTAR register
selected by the DSICTAS field in the DSPI_DSICR. Figure 25-25 shows the CSI Serialization logic.
25-44
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor